The engineer is engaged in the preparation of the tool infrastructure required for the design of VLSI components and his role is to provide the work environment required for the development of the components (Device Pcells) . In this role, he/she will develop PCELLS (Parametric cells) – a representation of basic components according to the definitions of the device engineer. It is the engineer’s responsibility to support the work environment by supporting the various software, integrating different EDA software, and writing plans when required to integrate them. The work is conducted in front of the other groups in the company – Inside the design center as well as the BU device teams in the factory.
Opportunity to take part in interesting and challenging projects: improve reliability, cost saving, safety.
The Senior FPGA Verification Engineer will be responsible for high reliably real-time FPGA verification activities.
High reliably FPGA logic design verification
High performance pipeline architectures verification
Verification of soft cores IP integration
Run unit verification tests for complex blocks
Run Top level verification tests (for all FPGA)
Support lab ramp up and tests
Run Code Coverage and Functional Coverage
Using Assertion-Based Verification
Run Direct, Random and stress tests
Lead and define Complex FPGA verification methodologies and tools
Development in conformance to safety and cybersecurity standard משרה 103092